1/7 AN1213 application note december 1999 emc testing . this evaluation section describes the noise immunity results. for reference, the test has been done as compar- ison between the tde1707-b , improved version and the previous one (old version). all of the statements regarding burst immunity refer to measurements done in esali (european system appli- cation lab industrial). the application laboratory is provided with an appropriate testing bench realised basing on directives contained in iec 801/4 normative. the correlated instrumentation consists of : - key tek ( thermo voltek ), ce master emc immunity test system : surge and burst generator. - tektronix tm502 : current probe - gould data sys 944 mhz - 500 ms/sec : digital storage oscilloscope - laboratory power supply ps-2403 : power supply the behaviour of the device was monitored with a current probe on the load, which seems to have less influence on the measurements. anyway it is important to pay attention because even when using a current probe it is really easy to couple additional noise, and of course the result consists in the achievement of lower immunity levels than the right ones: the fast transients should be coupled only thanks to the capacitive coupling clamp. for the same reason caution is mandatory regarding the power supply: this one should not be directly affected from the burst generator . additional coupling becomes easier and easier as the burst voltage increases: par- asitic antennas becomes more efficient. table 1. iec 801/4, limiting values of burst impulses testing configuration: old ( tde 1707) and new ( tde 1707 rev. b ) silicon have been tested and compared regarding fast transient ( burst ) immunity. this testing was performed on several layouts taking care to operate in the same test con- ditions. severity test voltage on signal line 42kv 31kv 20.5kv 1 0.25kv by matteo uccelli tde1707 noise immunity, short circuit and reverse output protection characterisation the tde1707 is a power switch ( i.p.s) especially dedicated to proximity detectors. for the characteristics of the i.p.s. please refer to the data sheet and an485. since the device operates in industrial environment, it is very important a good noise immunity. the overload (up to short circuit) and the output reverse connection hardiness are also key point for a device used in this applications.
AN1213 application note 2/7 the input pin was connected to vreg tanks to a 4,7 kohm resistor (r1), the device was supplying a 220 ohm resistor (r2) the cable to the load was a flat , parallel wires,2 m long cable. tests were performed with a power supply volt- age varying between 18 and 30 v. capacitors c4, c2 and c3 were smd ceramic capacitors, c1 was a ceramic no-smd capacitor (smd capacitor for c1 gives no benefits). on vcc (c4) a 100nf was used , while on vreg (c2) a 10nf was adopted, this for all of the tests. figure 1. bench exemplification figure 2. application schematic typically a burst exceeding the tolerance level causes the output transistor to switch off even if the input has not changed its high state. auxiliary equipment burst generator load insulation support capacitive coupling clamp eut ground reference plan signal and supply lines c1 x c2 10nf d1 led c3 x c4 100nf +v gnd 4 cap 3 hso 2 ld 1 lso 8 vss 7 vrg 6 in 5 u1 tde1707 r1 4.7 k r2 220
3/7 AN1213 application note figure 3. spurious transition of the output transistor due to burst pulse tde 1707 ( old silicon ): the value of the delay capacitor (c1) does not influence the immunity level of the device. the device behaves exactly the same whatever it is the value of the capacitor. without any other ca- pacitor than the two on vcc ( c4 ) and on vreg ( c2 ) the device shows an immunity level of +300 / -800. the immunity can improve if it is adopted a capacitor on the output ( c3 ). this capacitor has the same effect when- ever it is connected between ground and output or vcc and output. with c3=1 nf the immunity level is +1400 / -2500 v, c3=10 nf bring to an immunity level higher than +2500 /-2500. tde 1707 rev. b ( new silicon ): placing the delay capacitor (c1) results in lowering the fast transient immu- nity , which is anyway higher than the one acquired in the same conditions with the old silicon. in fact without capacitor on pin 3 the device is working correctly even with +2500 / -2500 v of burst voltage. this value is strongly reduced when a delay capacitor is adopted: with c1 = 470 pf, immunity drops to +600 / -1500 v. the same for higher values of c1 ( ex: 3.3nf ). even with tde1707 rev.b it is very useful to filter the output and 1 nf between ground and output (c 3) or between vcc and output it is sufficient to gain the correct operating of the device with a burst amplitude of +2500 / -2500. layout: anyway it must be underlined the importance of the layout . to gain the highest levels of immunity it is important to provide an accurate layout for the ground. star connection is recommended for the ground connec- tions of the capacitors on vcc and vreg.
AN1213 application note 4/7 figure 4. zoom of the layout table 2. immunity levels for old and new silicon corresponding to c out value short circuit and reverse output connection behaviour: the following evaluation refers to the tde 1707 rev. b operating with a supply voltage varying between 18 and 30 v, pure resistive load (from 0 to 15 k ohm ), ceramic capacitor on vcc ( 110 nf ) and vreg (10 nf ) the tde 1707 cannot withstand short circuit condition without a delay capacitor connected to pin 3. when the device is switched on from a cold state there is a zone corresponding to which the protection has no effect on the output transistor: pin 3 goes low but the output transistor does not switch off as it should. this zone becomes shorter and shorter with rising temperature and finally it is no longer present: when the device is switched on warm , the protection is fully working. this period of time in which the protection has no effect is long enough to have destroying effect on the device if the voltage supply is higher than 24 v. it is possible to see figure 5 this behaviour ( ch. 1 : vcc, ch. 3: pin 3, ch. 4: i out ). it is not possible to filter this effect directly on vcc and vreg , at least not for reasonable values of electrolytic capacitors paralleled to the ceramic ones. it is just sufficient to add a very small capacitor (68pf ) on pin 3 to have no longer this effect and to avoid the problem. cout (nf) tde1707 tde1707 rev. b no capacitor -800 / +300v -1500 / +600v 1nf -2500 / +1400v >(-2500 / +2500v) 10nf >(-2500 / +2500v) >(-2500 / +2500v)
5/7 AN1213 application note figure 5. short circuit protection failure at turn on (no capacitor on pin 3, device cold) figure 6. short circuit protection fully working (68pf on pin 3, device cold)
AN1213 application note 6/7 in case of reversal connection of the output (output of the device tied to supply ground and device ground to load - tested loads: from 0 to 15 k ohm) it is required a greater capacitor than in pure short circuit case (220 pf) in order to safely run the device. table 3. conclusions: table 2 well highlights the improvement, in terms of noise immunity, of the actual silicon version. moreover, us- ing the appropriate filters (this means: output capacitor, delay capacitor...), it is possible to safely use the tde1707 in its typical environment, and it results to be protected from possible injuries due to incidental wrong connections. worst case: short circuit reverse output connection minimal c delay value: 68pf 220pf
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